From: [email-masked]
To: "Rob Simcoe" <[email-masked]>
Cc: "Bill Forrest" <[email-masked]>, "Craig McMurtry" <[email-masked]>, "Judy Pipher" <[email-masked]>
Date: Wed, 9 Sep 2009 14:19:04 -0400 (EDT)

The basic issue is that we found fundamental changes in the appearance of
a pedestal frame with very minor changes in the default value of
Vbiasgate, as supplied by IDE.

The IDE default value of VBiasGate is 2.05 V.  We understand from Michael
that the current to the unit cell, entering through Vbiaspower and
controlled by Vbiasgate,  cannot be measured with the TIS
software.  (Test reports from Teledyne and U.Rochester with different array
controllers used values of Vbiasgate = 2.25 to 2.4 V lead to Vbiaspower
currents of 20 to 90 microamps). Interestingly, Christoph's software (for
32-output mode) that was optimized by TIS to run their arrays with a cold
SIDECAR uses Vbiasgate=2.1 V.

When we changed this value of Vbiasgate by only 10 mV, the appearance of
the pedestal frame completely changed.  The picture frame changed in
contrast from darker than most of the frame to brighter; a scratch-like
defect changed in darkness relative to the rest of the frame; the bright
"tree-rings" changed in contrast as well.  Does the default value of
Vbiasgate provided by IDE leave the array so close to a critical value,
that changing some other array bias is essential?

The unit cell currents quoted in the test report - are they to be divided
by the number of outputs?  Does running in the 32 output mode mean that the
supplied U.C. current should be set 8x higher, since all the tests in the
Test reports above used the 4 output mode?